RegViz: Visualize PCLKSEL0 Bitfield

NXP Semiconductors /LPC176x5x /SYSCON /PCLKSEL0

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Interpret as PCLKSEL0

PCLK_CAN2=CCLK_DIV_4, PCLK_UART0=CCLK_DIV_4, PCLK_TIMER1=CCLK_DIV_4, PCLK_ACF=CCLK_DIV_4, PCLK_SSP1=CCLK_DIV_4, PCLK_TIMER0=CCLK_DIV_4, PCLK_ADC=CCLK_DIV_4, PCLK_CAN1=CCLK_DIV_4, PCLK_I2C0=CCLK_DIV_4, PCLK_WDT=CCLK_DIV_4, PCLK_DAC=CCLK_DIV_4, PCLK_SPI=CCLK_DIV_4, PCLK_PWM1=CCLK_DIV_4, PCLK_UART1=CCLK_DIV_4

Description

Peripheral Clock Selection register 0.

Fields

PCLK_WDT	Peripheral clock selection for WDT. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8
PCLK_TIMER0	Peripheral clock selection for TIMER0. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8
PCLK_TIMER1	Peripheral clock selection for TIMER1. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8
PCLK_UART0	Peripheral clock selection for UART0. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8
PCLK_UART1	Peripheral clock selection for UART1. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8
RESERVED	Reserved.
PCLK_PWM1	Peripheral clock selection for PWM1. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8
PCLK_I2C0	Peripheral clock selection for I2C0. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8
PCLK_SPI	Peripheral clock selection for SPI. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8
RESERVED	Reserved.
PCLK_SSP1	Peripheral clock selection for SSP1. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8
PCLK_DAC	Peripheral clock selection for DAC. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8
PCLK_ADC	Peripheral clock selection for ADC. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8
PCLK_CAN1	Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_6): CCLK div 6. PCLK_peripheral = CCLK/6.
PCLK_CAN2	Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_6): CCLK div 6. PCLK_peripheral = CCLK/6,
PCLK_ACF	Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_6): CCLK div 6. PCLK_peripheral = CCLK/6

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